vishay siliconix sic730cd9 new product document number: 73670 s-62656?rev. c, 25-dec-06 www.vishay.com 1 fast switching mosfets with integrated driver features ? low-side mosfet control pin for pre-bias start-up ? undervoltage lockout for safe operation ? internal boostrap diode reduces component count ? break-before-make operation ? turn-on/turn-off capability ? compatible with any single or multi-phase pwm controller ? low profile, thermally enhanced powerpak ? mlf 9 x 9 package applications ? dc-to-dc point-of-load converters - 3.3 v, 5 v, or 12 v intermediate bus - examples - 12 v in /3.3 - 5 v out - 5 v in /1.5 - 3.3 v out ? servers and computers ? single and multi-phase conversion description the sic730cd9 is an integrated solution which contains two pwm-optimized mosfets (high side and low side mos- fets) and a driver ic. integratin g the driver allows better op- timization of power mosfets. this minimizes the losses and provides better performance at higher frequency. the sic730cd9 is packed in vishay siliconix?s high performance powerpak mlf 9 x 9 package. compact co-packing of com- ponents helps to reduce stray inductance, and hence in- creases efficiency. functional block diagram product summary input voltage range 3.3 to 24 v output voltage range 0.5 to 6 v operating frequency 100 khz to 1 mhz continuous output current up to 20 a peak efficiency 97.5 optimized duty cycle ratio 40 % p ower pak mlf 9 x 9 bottom view orderin g information: s ic7 3 0cd9-t1 figure 1. c boot v in sw v dd pwm cgnd v dd uvlo pgnd bbm sync shdn + -
www.vishay.com 2 document number: 73670 s-62656?rev. c, 25-dec-06 vishay siliconix sic730cd9 new product stresses beyond those listed under "absol ute maximum ratings" may cause permanent dam age to the device. these are stress rating s only, and functional operation of the device at t hese or any other conditions beyond those indi cated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating/condi tions for extended periods may affect device reliability. notes: a. see reliability manual for profile. the powerpak mlf 9 x 9 is a leadless package. the end of t he lead terminal is exposed co pper (not plated) as a result of the singulation process in manufacturing. a solder fillet at the expo sed copper tip cannot guaranteed and is not required to ensure adequate bottom side soldering interconnection. b. rework conditions: manual solder ing with a soldering iron is not recommended for leadless components. c. junction-to-case thermal impedance represents the effective th ermal impedance of all heat carr ying leads in parallel and is intended for use in conjunction with the thermal impedance of the pc board pads to ambient (r thja = r thjc + r thpcb-a ). it can also be used to estimate chip temperature if power dissipation and the lead temper ature of heat carrying (drain) lead is known. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol steady state unit logic supply v dd 7 v logic inputs v pwm 7.3 common switch node v sw 30 drain voltage v in 30 bootstrap voltage v boot sw + 7 maximum power sissipation (measured at 25 c) p d 6w operating junction and storage temperature range t j , t stg - 65 to 125 c soldering recommendations (peak temperature) a, b 225 recommended operating conditions parameter symbol steady state unit drain voltage v in 3.3 to 24 v logic supply v dd 4.5 to 5.5 input logic pwm voltage v pwm 5 bootstrap capacitor c boot 100 n to 1 f thermal resistance ratings parameter c symbol typical maximum unit maximum junction-to-case steady state r thjc 3.5 4.5 c/w maximum junction-to-ambient (pcb = copper 25 mm x 25 mm) r thja 60 75
document number: 73670 s-62656?rev. c, 25-dec-06 www.vishay.com 3 vishay siliconix sic730cd9 new product notes: a. pulse test; pulse width 300 ms, duty cycle 2 %. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. using application board sidb766706. specifications parameter symbol test conditions unless specified t a = 25 c 4.5 v < v dd < 5.5 v, 4.5 v < v in < 20 v limits unit min typ a max controller logic voltage v dd 4.5 5.5 v logic current (static) i dd(en) v dd = 4.5 v, sync = h, pwm = h, shdn = h 1200 a i dd(dis) v dd = 4.5 v, sync = h, pwm = h, shdn = l 120 logic current (dynamic) i dd1(dyn) v dd = 5 v, f pwm = 250 khz c 28 ma i dd2(dyn) v dd = 5 v, f pwm = 700 khz c 56 logic input logic input (vpwm) high v pwmh v dd = 5 v, sync = h, shdn = h 2.5 v low v pwml 1.35 logic input voltage (v sync )v sync v dd = 5 v, pmw = h, shdn = h 2.0 logic input voltage (v shdn )v shdn v dd = 5 v, pmw = h, sync = h 2.0 input voltage hysteresis (pwm) v hys 400 mv logic input current i shdn v dd = 5.5 v, shdn = 0 v 116 a i pwm v dd = 5.5 v, pmw = 5.5 v 114 protection break-before-make reference v bbm v dd = 5.5 v 2.4 v under-voltage lockout v uvlo v dd = 5 v, sync = h, shdn = h 3.5 4.1 4.25 under-voltage lockout hysteresis v h 0.4 mosfets drain-source voltage v ds i d = 250 a 30 32 v drain-source on-state resistance a r ds(on)1 v dd = 5 v, i d = 10 a high-side 8 10.4 m r ds(on)2 t a = 25 c low-side 3.6 4.32 diode forward voltage a v sd1 i s = 2 a, v gs = 0 v high-side 0.7 1.1 v v sd2 low-side 0.67 1.1 dynamic b, c tu r n o n d e l ay t i m e t d(on) 50 % - 50 % c 57 ns turn off delay time t d(off) 34
www.vishay.com 4 document number: 73670 s-62656?rev. c, 25-dec-06 vishay siliconix sic730cd9 new product timing diagram application information a (25 c, unless noted, lfm = 0) notes: a. experimental results using an evaluation board with a specific set of operating conditions. figure 2. shdn pwm sw t d(on) t d(off) sync hs mosfet gate ls mosfet gate figure 3. total efficiency 12 v in /3.3 v out figure 5. total efficiency 5 v in /2.5 v out 91 92 93 94 95 96 97 3 6 9 12 15 18 21 24 output current ? (a) ) % ( y c n e i c i f f e 500 khz 300 khz 700 khz 89 90 91 92 93 94 95 96 97 98 3 6 9 12 15 18 21 output current ? (a) ) % ( y c n e i c i f f e 500 khz 300 khz 700 khz figure 4. total loss 12 v in /3.3 v out figure 6. total loss 5 v in /2.5 v out 0 1 2 3 4 5 6 7 3 6 9 12 15 18 21 24 ) w ( s s o l l a t o t output current ? (a) 700 khz 500 khz 300 khz 0 1 2 3 4 5 6 7 3 5 7 9 11 13 15 17 19 21 ) w ( s s o l l a t o t output current ? (a) 700 khz 500 khz 300 khz
document number: 73670 s-62656?rev. c, 25-dec-06 www.vishay.com 5 vishay siliconix sic730cd9 new product pin configuration d n g p c boot powerpak mlf 9 mm 9 mm (bottom view) low-side mos tab (sw) high-side mos tab v in driver ta b cgnd 1 v in 2 v in 3 v in 4 v in 5 cgnd 6 c boot 7 8 v dd 9 v d d 0 1 v d d 2 1 d n g c 3 1 c n y s 4 1 n d h s 5 1 d n g p 6 1 2 3 v n i 1 3 v n i 0 3 v n i 9 2 w s 8 2 w s 7 2 w s 6 2 w s 5 2 w s 24 pgnd 23 pgnd 22 pgnd 21 pgnd 20 pgnd 19 pgnd 18 pgnd 17 pgnd 1 1 m w p truth table shdn sync pwm hs mosfet ls mosfet lxxoffoff hlloffoff hlhonoff hhloffon hhhonoff pin description pin number symbol description 1 - 4, 30 - 32 v in input-voltage (high-side mosfet drain) 5, 12 cgnd control ground. shoul d be connected to pgnd externally 6, 7 c boot connection pin for bootstrap c apacitor for high-side mosfet 8, 9, 10 v dd logic supply voltage - decoupling to g nd with a cap is strongly recommended 11 pmw pulse width modulation (pwm) signal input 13 sync disable low-side mosfet drive 14 shdn disable all functions (active low) 15 - 24 pgnd power ground (low-side mosfet source) 25 - 29 sw connection pin for output inductor (hi gh-side mosfet source/low-side mosfet drain)
www.vishay.com 6 document number: 73670 s-62656?rev. c, 25-dec-06 vishay siliconix sic730cd9 new product device operation pulse width modular (pwm) this is a cmos compatible logic input that receives the drive signals from the controller circuit. the pwm signal drives the buck switch. break-before-make (bbm) the sic730cd9 has an intrenal break-before-make function to ensure that both high-side and low-side mosfets are not turned on the same time. the low-side mosfet will not turn on until the high-side gate driv e voltage is less than vbbm, thus ensuring that the high-si de mosfet is turned off. this parameter is not user adjustable. shdn cmos logic signal. in the low state, the shdn disables both high-side and low-side mosfet?s. capacitor to boot input (c boot ) connected to v dd by an internal diode via the c boot pin, the boot capacitor is used to sust ain rail for the high-side mos- fet gate drive circuit. under voltage lockout (uvlo) during the start up cycle, the uv lo disables the gate drive holding high-side and low-side mosfet?s low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. the uvlo is not user adjustable. sync pin for pre- bias start-up the low side mosfet can be individually enable or dis- abled by using the sync pin. in the low state (sync = low), the low-side mosfet is turned off. in the high state, the low-side mosfet is enabled and follows the pwm input signal (see timing diagram, figure 2). sync is a cmos compatible logic input and is used for a pre?biased output voltage. voltage input (v in ) this is the power input to the drain of the high-side power mosfet. this pin is connected to the high power intermedi- ate bus rail. switch node (sw) the switch node is the circuit pwm regulated output. this is the output applied to the filter circuit to deliver the regulated high output for the buck converter. power ground (pgnd) this is the output connection from the source of the low-side mosfet. this output is the gr ound return loop for the power rail. it should be externally connected to cgnd. control ground (cgnd) this is the control voltage return path for the driver and logic input circuitry to the sic730cd9. this should externally con- nected to pgnd. application circuit the sic734cd9 has a built-in delay time that is optimized for the mosfet pair. when the pwm signal goes low, the high- side driver will turn off, after circuit delay (t doff ), and the out- put will start to ramp down, (t f ). after a further delay, the low- side driver turns on. when the pwm goes high, the low-side driver turns off, (t don ). as the body diode starts to conduct, the high-side mosfet turns on after a short dalay. the delay is minimized to limit body diode conduction. the output then ramps up, (t r ). cgnd 5 v 3.3 v to 20 v mosfet drive circuitry with break-before- make c boot v in sw c boot l + pgnd cgnd shdn v dd q 1 q 2 dc-dc controller v out pwm sync power up sequence : the presence of v dd prior to applying the v in and pwm is recommended to ensure a safe turn on power down sequence: the sequence should be reverse of the on sequence, turn off the v in before turning off the v dd . pgnd hs ls figure 7.
vishay siliconix sic730cd9 document number: 73670 s-62656?rev. c, 25-dec-06 www.vishay.com 7 new product typical application vishay siliconix maintains worldwide manufac turing capability. products ma y be manufactured at one of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?73670. figure 8. v in v dd sync shdn cgnd c boot sw pgnd pwm sic730cd9 v in v dd sync shdn cgnd c boot sw pgnd pwm sic730cd9 v in v dd sync shdn cgnd c boot sw pgnd pwm sic730cd9 v in v dd sync shdn cgnd c boot sw pgnd pwm sic730cd9 v out pwm1 pwm2 pwm3 pwm4 pwm control circuit 5 v 12 v
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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